Master’s student in Embedded Systems, currently pursuing my Master thesis verification Environment using UVM for NoC based architecture". I worked as a Component Design Engineer at Intel Technologies, India for 5 years, prior to my Masters. Seeking a job in ASIC design or verification position.
Spin Digital Video Technologies March 2015 - August 2015Research Experience:
Analyzed the performance of HEVC/H.265 encoder and decoder.
Developed scripts to run benchmarking and performance analysis.
Documented the results of the performance analysis.
Component Design Engineer
Intel Technologies India Pvt Ltd November 2009 - August 2014 Wrote test plans and test cases to verify micro architectural features of cache coherency and memory ordering for multicore processors – NHMEx, WSMEx, Jaketown and Ivytown.
Developed several python based harassers to validate Memory RAS features for various processors like Jaketown, Ivytown.
Validated Quick Path Interconnect and Cache Coherency error injection DFx in NHMEx and WSMEx.
Developed test content to verify correctable and un-correctable error injection hardware designs. Validated Memory ECC error injection logic.
Validated Memory ECC, SDDC, DDDC, Spare and Mirroring Engine logic for Ivytown processor
Developed an error injection framework named RASCAL which is a rapid/random RAS error injection framework in the SVOS environment. Written in C++ with inherited class-based design to promote reuse.
Developed an Intel specific Random Test Generator tool to validate multicore processors like Ivytown, Jaketown processors..