• IP Logic Design Engineer

    at Intel

    March 2018 - at Present


    -USB subsystem owner, perform logic design, RTL coding, and generate cell libraries and functional units to build up a subsystem that contains the external USB controller and PHY IPs. -Build and run module-level test-bench and simulation to make sure the reliability and functionality of external IPs. -Run SPYGLASS lint and CDC rules to avoid design errors and timing violations of clocks and resets. -Work closely with the backend team for clock tree information, and constraint generation review for the synthesis. -Work closely with the DFT team for scan insertion. -Build and run the SOC level test-bench to perform the SOC verification, make sure the USB subsystem can meet the protocol. -Run the GLS with a synthesis netlist and different corner case SDF to perform dynamic verify of timings and behaviors. -Participate in the development of Architecture and Micro-architecture specifications for the subsystem.

  • Probe Functional Test Engineer

    at Micron

    June 2017 - December 2017


    -Developed and maintained wafer-level functional test strategies and programs for semiconductor NAND Flash products. -Provided cost-effective and innovative solutions for production test flows, interface hardware and test equipment, redundancy analysis schemes, data reporting, and monitoring, and optimizing of device yields. -Collaborated with various engineering, equipment, and production groups to optimise and automate equipment and processes to minimise costs and to improve quality.

  • Project Engineer Intern

    at Intel

    July 2016 - April 2017


    -Developed a VERILOG hierarchy parser by using Perl script language. -According to the IEEE 802.3 standard, designed and implemented MAC frame packet generator and receiver which supported both GMII and XGMII interfaces. A UVM verification environment was also built to verify the functionalities of the generator and receiver. -Designed and implemented a fully synthesizable test-bench to ascertain that the coding gain of a delivery low-density parity-check (LDPC) decoder IP was as required by the 2.5G Ethernet system. A log-likelihood ratio (LLR) channel demodulator was also designed and implemented in the test-bench.


  • Master Student of Integrated Circuit Design

    at Nanyang Technology University

    2015 - 2017 (2 years) Singapore

  • Master Student of Integrated Circuit Design

    at Technical University of Munich

    2015 - 2017 (2 years)

  • BEng Electronic Engineering

    at University of Southampton

    2012 - 2015 (3 years) Hampshire


  • English Negotiation