- Entry level
- No Education
- Salary to negotiate
- Experience in ASIC Physical Design RTL to GDSII Implementation flow
- Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc.
- Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal)
- Knowledge of Timing .lib generation, Physical View Generation (LEF, GDS, CEL, FRAM, NDM etc.)
- Physical Verification (DRC/LVS/Density/Antenna etc.)
- Reliability Verification (EM/IR drop etc.)
- Well versed with TCL/Perl/Shell Scripting
- EDA tool knowledge: Design Compiler, ICC/ICC2, StarRC-XT, Primetime, ICV
- Tape out experience
Inside this Business Group
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.
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About the company
Intel is a place where employees can pursue their passions, support world-changing initiatives, and thrive intellectually.
Our employees are as diverse as our customers, vendors, and colleagues in the global market. This worldwide perspective helps us anticipate, and provide for, the growing needs of a changing marketplace. Here are a few examples:
The collaboration of Intel teams halfway across the world from each other was key to the development of our Intel® Centrino® processor technology.
The leaders of our Technology and Manufacturing Group use diversity to broaden team perspective on projects.
Our International Summit for Proliferating Ideas and Recognizing Excellence lets innovators from every country within Intel Corporate Services share ideas.