- Entry level
- No Education
- Salary to negotiate
Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
BS degree in Electrical Engineering or related field of study with a minimum of 10 years of relevant experience in SoC/IP Uarch, design, Verification or MS degree with 8+ years of directly related industry experience. The proficient candidate should have experience on multimillion Gate and complex Design with multiple clocks and power domains. Understanding of the design issues in the RTL Experience and working knowledge of HVLs (SV UVM/C/C++), HDLs (Verilog), PLI/DPI. Ability to debug complex issue. GLS ownership and deliverables involves Developing methodology and executes 'Gate Level Simulation' (GLS) for IP/SoC designs, Carry out pre-routed and post routed simulation with SDF both at block and SOC level, Iterate through the process to achieve GLS exit criteria. Ability to script and automate the process is an added plus. Testbench and Testplan development background.
Inside this Business Group
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About the company
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