Job description


  • Entry level
  • No Education
  • Salary to negotiate
  • Bangalore


Come join Intel's Platform Engineering Group organization as an DFX Design Engineer. In this role you will understand DFT/Test architectures, integrate DFT infrastructure (TAP controller, VISA etc) into SOC, implement DFT/Test in designs in the area of DFT Synthesis, generate test patterns using industry standard tools, analyze and drive the improvements to test coverage, run/debug Gate level DFT simulation. Work also will include providing DFT constraints/exceptions to Static Timing Analysis (PV) and coordination of Scan/ATPG collaterals with IP providers

- 8 years' experience in implementing DFT/Test in designs
- Understanding of DFT Infra, ATPG process, scan compression, MBIST,..
- Understanding of STA process, constraints for various DFT modes
- independent problem solving, debugging various simulation failures, formal verification etc.
- Understanding of Intel specific Debug architectures (e.g. VISA), Debug Infra (north peak etc) will be a major plus.
- Understanding of Intel's specific IO DFX (loop back etc) and IDV methodology will be a major plus
- Understanding of Scan/ATPG collaterals


Engineering Degree

Inside this Business Group
The Core and Visual Computing Group (CVCG) is responsible for the architecture, design and development of the CPU core and visual technology IPs that are central to Intel's system-on-a-chip (SoC) products and key to our datacenter, client and Internet-of-Things (IOT) platforms. CVCG strives to lead the industry through continuous innovation and world class engineering.

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About the company

Intel is a place where employees can pursue their passions, support world-changing initiatives, and thrive intellectually.

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