Job description


  • Entry level
  • No Education
  • Salary to negotiate
  • Hyderabad


In this job the Candidate shall be responsible for EITHER of the description below :

- You will be responsible for ASIC Physical Design RTL to GDSII Implementation. Your tasks may include but not limited to Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill etc. Low power design closure (UPF based implementation) skills are must and associated sign-off (SG-LP/VCLP/Conformal) are preferred. Strong basics in timing is must. Knowledge in the areas of timing model generation, physical verification & EMIR is preferred.

- You will be responsible for STA and timing closure activities of Intel SoCs/Partitions. Your tasks may include but not limited to Understanding of Design, Architecture and Clocking, Interaction with FE/DFT/Verification teams, Writing constraints, understanding synchronous & asynchronous paths, Clock domain crossing issues, Timing closure, Generating timing ECOs Timing signoff & Debugging/troubleshooting of timing issues in a design.

- You will be responsible for Physical Sign-Off Verification Team and resolve problems related to DRC, LVS, ERC, FC Integration and TapeOut. You would be needed to manage Physical Sign-Off of partitions as well as SoC. You would be contributing in any activities related to methodology development in Physical Verification Domain.

- You will be part of LEC/LP Sign-Off Team. You would be responsible for debugging complex issues related to LEC and Low Power both at partition level and SoC. You would be interacting with Hard-Macro teams as well as methodology teams to define LEC/LP constraints. Additional experience in Low Power Logical Equivalence is added advantage.

- You shall be responsible for part of the Power Delivery team where you shall be defining the Power Grid for a complex SoC. You shall be responsible to Sign-Off the SoC for IR Checks (Vectored or Vectorless) which includes Static, Dynamic, Ramp-up Analysis. You would be needed to manage both partition level as well at SoC Level.

-You will be part of Power Estimation team where besides estimation you shall be needed to drive state-of-art Power Optimization methodologies to reduce overall dynamic/leakage power for SoC. Interactions with Power Architecture teams, understanding of power Architecture and devising new strategies shall be needed in addition to contribution to estimating power at SoC Level.

Additional skills include:
- Hands-On experience with domain relevant industry standard tools like ICC, ICCII, Primetime, Redhawk, ICV, Calibre, Conformal, Spyglass-LP, Power Artist Etc.
- Good understanding and exposure of overall SoC Cycle.
- Good scripting skills in TCL/Perl/Shell to automate tool/flow methodologies.
- You must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a
diverse team environment.
- You shall be self-motivated with the initiative to seek constant improvements and driving new methodologies in the domain expertise.


You must possess a Bachelor of Engineering degree or Master of Engineering in Electrical and/or Electronics Engineering with 7+ Years of relevant experience with the skills in all/either Physical Implementation, Timing Closure, LEC, PDN or Physical Verification .

Inside this Business Group

Other Locations

India, Bangalore

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About the company

Intel is a place where employees can pursue their passions, support world-changing initiatives, and thrive intellectually.

Our employees are as diverse as our customers, vendors, and colleagues in the global market. This worldwide perspective helps us anticipate, and provide for, the growing needs of a changing marketplace. Here are a few examples:

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