- Entry level
- No Education
- Salary to negotiate
Deep learning has in recent times risen as the state-of-the-art within certain areas, e.g. image classification. In order to utilize these algorithms in the field there needs to be a go to inference accelerator ready to apply pre-trained models. Image classification algorithms are highly parallelizable in nature which suits the FPGA very well. However, optimizing the compute cores to be run in parallel together with the architecture deploying these requires thorough investigations.
The task is to build a specialized VHDL/Verilog compute core for Deep Learning image processing. This means implementing convolution, ReLU and maxpooling for multiple data and parameter bit sizes, as well as obtaining a scaling of the number of hardware resources as a function of bit sizes. Additionally, one shouldcompare the implementation to one generated using a naïve high-level synthesis (HLS)implementation.
We are looking for a candidate with at least some background in electrical engineering and good programming skills. The applicant should be on his/her way to becomming an FPGA rockstar.
The following skills are meriting (but not necessary):
- C/C++ programming
- Machine learning basics
- Image processing
Apply by sending your resume to firstname.lastname@example.org. Mark e-mail with "Deep Learning Inference on FPGAs".
For any and all questions, call Viktor (+46 76-174 29 02) or August (+46 708 68 85 04).
Note that Synective have offices in Stockholm, Linköping and Gothenburg. The student should be located at aSynective office, in order to ease the communication between student and supervisor.