- Entry level
- No Education
- Salary CN¥50,000.00 - CN¥80,000.00 gross per year
This is an exciting opportunity for a experienced Senior Verification Engineer to join our client, a leading international high technology company who create cutting-edge solutions to improve the quality of life with green, easy-to-use products, and dedicated for system-level solution that optimise its customers' applications.
This role is located Shanghai. As the Senior Verification Engineer, you will be in a position within the sensor product design team. Responsibilities focus on developing and implementing architectures for IC products.
Our client thrives on re-imagining and re-defining the possibilities of high-performance power solutions in the communications, computing, consumer, automotive and industrial segments.
Verification planning, maintenance, feature extraction, verification test case and checker development
* Improving efficient, reusable state-of-the-art verification environments and testbench structures
* Operating the system Verilog, UVM verification methodology, and coding related programs as required
* Leading the digital verification of mixed signal ICs or sub-systems
* Working closely with the Analog Mixed Signal (AMS) verification and Analog Design team
* Degree from EE. CS and ME and good plus with qualifications from circuit design
* Hand on experience in design verification, and skilled in standard ASIC design and verification tools and flow.
* Had good working knowledge from DDR protocol and computer system architecture.
* Experienced in Perl and shell programming would be an added advantage.
* Had good knowledge in ASIC/FPGA design process and verification tools.
* Skilled in design and verification languages (Verilog, System Verilog, SVA etc.).
* Fluent communication in English and Chinese.
* Good team player
For a confidential discussion please contact Nick Chen at IC Resources.