Job description

Requirements

  • Entry level
  • No Education
  • Salary to negotiate
  • Cambridge

Description

Contract Verification Engineer

polkadotfrog are currently recruiting for a UVM Verification Engineer on a contract basis for 10 months where you will be working onsite in Cambridge. You will be working closely with a team working on UVM based verification of a complex multi unit System IP product.

This new contract will require applicants to have extensive experience of designing and implementing verification environments for complex RTL designs. You will be well-versed in the use of class based hardware verification languages e.g. SystemVerilog or Specman 'e.' You will have detailed knowledge of Verification methodologies such as UVM and an in-depth understanding of end-to-end verification processes, from test plan creation through to verification closure.

Applications will have an understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioural functional models. You will have the ability to quickly understand and apply complex specification detail and ideally have familiarity with Mentor Questasim simulator, Synopsys VCS & Cadence. The system that would be worked by the contractor would be able to run on these simulators.

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  • hardware