Job description

Requirements

  • Entry level
  • No Education
  • Salary to negotiate
  • Cambridge

Description

Must be a with an active Secret Security Clearance.Position: Senior Digital Design Verification EngineerLocation: Cambridge, MACompensation: $125,000 - $160,000 + Excellent Benefits + Paid RelocationJob Description:This Client is seeking a motivated and experienced Senior Verification Engineer to tackle novel verification challenges in FPGAs and ASICs.You will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.You will develop verification approaches, author and execute verification plans, and use formal analysis tools.You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects.Join this Client as they develop the next generation of digital and embedded hardware platforms.Qualifications:BS degree required.6+ years of experience.Fluent in SystemVerilog including SVA.Recent experience with UVM.Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS).Firm grasp of constrained-random and coverage-driven verification.Experience with formal analysis.Practice using Python, Perl, Bash or other scripting languages.Ability to work in a Linux environment.Strong analysis and problem-solving skills.Preferred Skills:Experience leading verification teams.Experience with analog or mixed-signal simulations (AMS).Permanent

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