Job description


  • Entry level
  • No Education
  • Salary to negotiate
  • Mountain View


Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

As a Debug Architect, you'll lead the architectural definition/configuration of the Debug, Trace, and Performance Monitoring subsystem for heterogeneous compute elements in an AMBA-based SoC product. You'll collaborate with software and hardware architects to build a compelling design and justify your decisions with the performance of relevant workloads. Utilizing your Arm and Tensilica-specific knowledge, you will support the configuration and integration of compute cores into the overall design, including working with the power, clock, reset, security, and all other related architects.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Minimum qualifications:

- Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.

- 7 years of experience.

- Experience with Arm and Cadence Tensilica architectures (CPU/DSPs, fabric, bus protocols, debug and trace).

Preferred qualifications:

- Master's degree or PhD in Computer Science or Electrical Engineering.

- 15 years of experience.

- Experience with most of the following: multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS)/AVS, etc.

- Experienced debug, trace, and performance profiling architect and micro-architect.

- Knowledge of MIPI standards related to Debug and Trace.

- Define the Debug, Trace, and Performance Monitoring architecture of SoCs, authoring chip architecture (and sometimes micro-architecture) specifications.

- Collaborate with company-wide stakeholders like Product Management, System Architecture, and Software Engineering to come up with a detailed Debug,Trace, and Performance Monitoring SoC feature set.

- Understand device usage scenarios and help drive tradeoffs. Perform PPA (performance, power, area) evaluation of prospective IPs and sub-systems.

- Work closely with design, verification, physical design, and silicon validation teams to ensure the implementation follows the architectural and micro-architectural intent.

- Monitor relevant industrial and academic trends.

About the company

Google is not a conventional company, and we don't intend to become one. True, we share attributes with the world's most successful organizations - a focus on innovation and smart business practices comes to mind - but even as we continue to grow, we're committed to retaining a small-company feel. At Google, we know that every employee has something important to say, and that every employee is integral to our success.

We provide individually-tailored compensation packages that can be comprised of competitive salary, bonus, and equity components, along with the opportunity to earn further financial bonuses and rewards. Googlers thrive in small, focused teams and high-energy environments, believe in the ability of technology to change the world, and are as passionate

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